(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a high Q inductor by reducing the energy loss that is typically encountered by rf inductors that are employed in silicon Integrated Circuits.
(2) Description of the Prior Art
Electronic circuitry can be divided into two broad fields, one field addresses digital processing while the second field addresses the manipulation of analog signals. The vast majority of semiconductor devices that are fabricated have as function the manipulation or storage of digital information, a function that is handled by on-off conditions of switching transistors or the presence or absence of an electrical charge on capacitive components. There is however, in addition, a field of semiconductor applications that addresses the processing of analog signals. The functions of analog electronic circuitry have in previous years typically been handled by separate components such as relatively large capacitors or relatively large inductors. The separate components may have been applied in combination with digital processing capabilities whereby however a significant portion of the functional implementation has been realized by the use of for instance capacitive and inductive components in addition to and functionally collaborating with the digital components. Circuit requirements that are imposed on components that are required for analog processing have in the past limited the integration of such components into typical semiconductor integrated circuit devices.
In addition, semiconductor devices can be integrated for the creation of Radio Frequency (RF) amplifiers. A major component of typical RF amplifiers is a tuned circuit that contains inductive and capacitive components. The tuned circuit has as electrical characteristic that, dependent on and determined by the values of the inductive and capacitive components, can form an impedance that is frequency dependent which enables the tuned circuit to either form a high or a low impedance for signals of a certain frequency. In this manner the tuned circuit can either reject or pass and further amplify components of an analog signal based on the frequency of that component. This tuned circuit can therefore be used as a filter to filter out or remove signals of certain frequencies or to remove noise from a circuit configuration that is aimed at manipulating analog signals. The tuned circuit can also be used to form a high electrical impedance by using the LC resonance of the circuit and to thereby counteract the effect of parasitic capacitances that form part of a circuit. The selfresonance that is caused by the parasitic capacitance between the (spiral) inductor and the underlying substrate will limit the use of the inductor at high frequencies.
The integration of functions of analog data manipulation and analog data storage with the functions of digital data manipulation and digital data storage on one semiconductor monolithic substrate offers a number of significant advantages. For instance, manufacturing costs can be significantly reduced while power consumption for the combined functions is also reduced. As previously indicated, inductors however can typically be of significant size and therefore require a significant area of the semiconductor device to be implemented. To limit the impact of space requirements that the creation of an inductor imposes on the surface of a semiconductor device, inductors are typically formed on the surface of a substrate in a spiral form. The spiral form of the inductor however results in parasitic capacitances between the inductor wiring and the underlying substrate, due to the physical size of the inductor. These parasitic capacitances have a serious negative effect on the functionality of the created LC circuit by sharply reducing the frequency of resonance of the tuned circuit of the application.
A measure of the applicability of a created inductor that is used in the industry is the Quality factor of the inductor. The quality factor Q of an inductor is defined as follows: Q=Es/El wherein Es is the energy that is stored in the reactive portion of the component while El is the energy that is lost in the reactive portion of the component. The higher the quality of the component, the closer the resistive value of the component approaches zero while the Q factor of the component approaches infinity. The quality factor for components differs from the quality that is associated with filters or resonators. For components, the quality factor serves as a measure of the purity of the reactance (or the susceptance) of the component which can be degraded due to parasitics. In an actual configuration, there are always some physical resistors that will dissipate power thereby decreasing the power that can be recovered. The quality factor Q is dimensionless. A Q value of greater than 100 is considered very high for discrete inductors that are mounted on the surface of Printed Circuit Boards. For inductors that form part of an integrated circuit, the Q value is typically in the range between about 3 and 10.
In creating an inductor on a monolithic substrate on which additional semiconductor devices are created, the parasitic capacitances that occur as part of this creation limit to about 10 the quality factor that can be achieved for the inductor using the conventional silicon process. This limitation is, for many applications, not acceptable. Dependent on the frequency at which the LC circuit is designed to resonate, significantly larger values of quality factor, of for instance 100 or more, must be available. Prior Art has in this been limited to creating values of higher quality factors as separate units, and in integrating these separate units with the surrounding device functions. This negates the advantages that can be obtained when using the monolithic construction of creating both the inductor and the surrounding devices on one and the same semiconductor substrate. The non-monolithic approach also has the disadvantage that additional wiring is required to interconnect the sub-components of the assembly thereby again introducing additional parasitic capacitances and resistive losses over the interconnecting wiring network. For many of the applications of the RF amplifier, such as portable battery powered applications, power consumption is at a premium and must therefore be as low as possible. By raising the power consumption, the effects of parasitic capacitances and resistive power loss can be partially compensated but there are limitations to even this approach. These problems take on even greater urgency with the rapid expansion of wireless applications such as portable telephones and the like. Wireless communications is a rapidly expanding market where the integration of RF integrated circuits is one of the most important challenges. One of the approaches is to significantly increase the frequency of operation to for instance the range of 10 to 100 GHz. For such high frequencies, the values of the quality factor obtained from silicon-based inductors are significantly degraded. For applications in this frequency range, monolithic inductors have been researched using other than silicon as the base for the creation of the inductors. Such monolithic inductors have for instance been created using sapphire or GaAs as a base. These inductors have a considerably lower parasitic capacitance than their silicon counterparts and therefore provide higher frequencies of resonance of the LC circuit. Where however more complex applications are required, the need still exists to create inductors using silicon as a substrate. For those applications, the approach of using a base material other than silicon has proven to be too cumbersome while for instance GaAs as a medium for the creation of semiconductor devices is as yet a technical challenge that needs to be addressed.
The incorporation of RF inductors without sacrificing device performance due to substrate losses has been extensively researched in recent years. Some of the techniques that have been used for this approach include:
the selective removing (by etching) of the silicon underneath the inductor (using methods of micro-machining) PA1 using multiple layers of metal (such as aluminum) interconnects or of copper damascene interconnects PA1 using a high resistivity silicon substrate PA1 employing biased wells underneath a spiral conductor PA1 inserting various types of patterned ground shields between the spiral inductor and the silicon substrate PA1 increasing the thickness of the inter-layer dielectric. PA1 1) enhance the quality (Q) value of the inductor, and PA1 2) increase the frequency of the LC self-resonance thereby increasing the frequency range over which the inductor can be used.
The above listing of researched alternatives is not meant to be complete or all inconclusive. All of the above approaches have as common objectives to:
The invention addresses the effect that the series spreading resistance associated with the substrate will degrade the Q factor of the inductor thereby affecting the usefulness of a monolithic or integrated inductor that is implemented on silicon substrates. This effect can be overcome if the area underneath the inductor can be made to appear locally insulating by selectively removing the underlying silicon resulting in inductors that are suspended. The inductor of the invention is created above regions of Shallow Trench Isolation (STI) whereby the negative impact that an underlying layer of silicon has is further reduced by creating the inductor in a location that is (relatively far) removed from active circuitry in the surface of the substrate.
The creation of high density semiconductor packages frequently requires the use of Chip on board (COB) techniques that are used to attach semiconductor die to a Printed Circuit Board (PCB). The types of die attachments that are typically used to connect a die to a PCB include flip chip attachment, wirebonding, and tape automated bonding (TAB). The invention addresses the formation of inductors that can be applied together with flip chip attachment to a PCB or other substrate. A flip chip is a semiconductor chip that has an array of connect points spaced around an active surface of the flip chip, the flip chip is mounted face down to a substrate. The electrical connect points that are used for flip chip connections can be a Ball Grid Array (BGA) arrangement (wherein an array of minute solder balls is arranged on the surface of the flip chip that attaches to the substrate), a Slightly Larger than Integrated Circuit Carrier (SLICC) (which is similar to the BGA but has a smaller solder ball pitch and a smaller diameter than the BGA) and a Pin Grid Array (PGA) (whereby an array of small pins extends perpendicularly from the attachment surface of a flip chip, such that the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment). The flip chip is bonded to the substrate by reflux or reflow of the solder balls. The solder balls may also be replaced with a conductive polymer.
U.S. Pat. No. 5,541,135 (Pfeifer et al.) shows a multi chip module having an inductor on the top polyimide layer of the flip chip.
U.S. Pat. No. 5,747,870 (Pedder) shows a flip chip assembly with an inductor on the polyimide.
U.S. Pat. No. 6,005,466 (Pedder) shows a flip chip assembly with an inductor on the polyimide.
U.S. Pat. No. 5,973,391 (Bischoff et al.) shows an inductor in a package.
U.S. Pat. No. 5,611,008 (Yap) shows a microwave package with the inductor under the surface.